View SC480_8226443.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

www.semtech.com 1 power management SC480 complete ddr1/2/3 memory power supply november 3, 2006 description features the SC480 is a combination switching regulator and linear source/sink regulator intended for ddr1/2/3 memory systems. the purpose of the switching regulator is to generate the supply voltage, vddq, for the memory system. it is a pseudo- xed frequency constant on- time controller designed for high ef ciency, superior dc accuracy, and fast transient response. the purpose of the linear source/sink regulator is to generate the memory termination voltage, vtt, with the ability to source and sink a 3a peak current. for the vddq regulator, the switching frequency is constant until a step in load or line voltage occurs at which time the pulse density, i.e., frequency, will increase or decrease to counter the transient change in output or input voltage. after the transient, the frequency will return to steady-state operation. at lighter loads, the selectable power-save mode enables the pwm converter to reduce its switching frequency and improve ef ciency. the integrated gate drivers feature adaptive shoot-through protection and soft-switching. additional features include cycle-by-cycle current limiting, digital soft-start, over-voltage and under- voltage protection and a power good ag. for the vtt regulator, the output voltage tracks ref, which is ? vddq to provide an accurate termination voltage. the vtt output is generated from a 1.2v to vddq input by a linear source/sink regulator which is designed for high dc accuracy, fast transient response, and low external component count. all three outputs (vddq, vtt and ref) are actively discharged when vddq is disabled, reducing external component count and cost. the SC480 is available in a 24-pin mlpq (4x4 mm) package. constant on-time controller for fast dynamic response on vddq ddr1/ddr2/ddr3 compatible vddq = fixed 1.8v or 2.5v, or adjustable from 1.5v to 3.0v 1% internal reference (2% system accuracy) resistor programmable on-time for vddq vcca/vddp range = 4.5v to 5.5v vin range = 2.5v to 25v vddq dc current sense using low-side r ds(on) sensing or external r sense in series with low-side fet cycle-by-cycle current limit for vddq digital soft-start for vddq analog soft-start for vtt/ref smart over-voltage vddq protection against source- current loads combined en and psave pin for vddq over-voltage/under-voltage fault protection power good output separate vcca and vddp supplies vtt/ref range = 0.75v ? 1.5v vtt source/sink 3a peak internal resistor divider for vtt/ref vtt is high impedance in s3 vddq, vtt, ref are actively discharged in s4/s5 24 lead mlpq (4x4 mm) lead-free package fully weee and rohs compliant ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? notebook computers ? cpu i/o supplies ? handheld terminals and pdas ? lcd monitors ? network power supplies applications typical application circuit ref r7 10r c10 1uf vtt c8 0.1uf q1 q2 d1 c3 2x10uf vbat r1 1meg l1 + c6 vddq vtt_en r6 10r c9 1uf vbat c7 1nf c1 1uf en/psv c4 10uf pgnd2 1 vtts 2 vssa 3 ton 4 ref 5 vcca 6 nc 7 vtten 10 fb 9 lx 20 dl 19 pgnd1 18 pgnd1 17 ilim 16 vddp 15 vddp 14 nc 12 en/psv 11 vddqs 8 pgd 13 vttin 23 vtt 24 bst 22 dh 21 pad u1 SC480 r4 vddq 5v vttsns pad c2 0.1uf 5v pgood rilim c11 1uf c5 10uf vddqvddq
2 ? 2006 semtech corp. www.semtech.com power management SC480 power management electrical characteristics exceeding the speci cations below may result in permanent damage to the device or device malfunction. operation outside of the parameters speci ed in the electrical characteristics section is not implied. exposure to absolute maximum rated conditions for extended periods of time m ay affect device reliability. test conditions: v in = 15v, vcca = vddp = vtten = en/psv = 5v, vddq = vttin = 1.8v, r ton = 1m . t amb = -40 to +85c. parameter symbol maximum units ton to vssa -0.3 to +25.0 v dh, bst to pgnd1 -0.3 to +31.0 v bst, dh to lx -0.3 to +6.0 v lx to pgnd1 -2.0 to +25.0 v dl, ilim, vddp to pgnd1 -0.3 to +6.0 v vddp to dl -0.3 to +6.0 v vttin to pgnd2; vtt to pgnd2; vttin to vtt -0.3 to +6.0 v en/psv, fb, pgd, ref, vcca, vddqs, vtten, vtts to vssa -0.3 to +6.0 v vcca to en/psv, fb, ref, vddqs, vtt, vtten, vttin, vtts -0.3 to +6.0 v pgnd1 to pgnd2; pgnd1 to vssa; pgnd2 to vssa -0.3 to +0.3 v thermal resistance junction to ambient (1) ja 29 c/w operating junction temperature range t j -40 to +150 c storage temperature range t stg -65 to +150 c peak ir re ow temperature, 10s - 40s t pkg 260 c esd protection level (2) v esd 2kv parameter conditions 25c -40c to 85c units min typ max min max input supplies vcca operating current s0 state (vtt on); en/psv = vcca; fb > regulation point, ivddq = 0a 1500 2500 a vcca operating current s3 state (vtt off); en/psv = vcca; fb > regulation point, ivddq = 0a 800 1400 a vcca operating voltage 5 4.5 5.5 v vddp operating current fb > regulation point, ivddq = 0a 70 150 a ton operating current rton = 1m 15 a vttin operating current ivtt = 0a 1 5 a vcca + vddp + ton shutdown current en/psv = vtten = 0v 5 11 a vttin shutdown current en/psv = vtten = 0v 1 a notes: 1) calculated from package in still air, mounted to 3? x 4.5?, 4 layer fr4 pcb with thermal vias under the exposed pad per jesd 51 standards. 2) tested according to jedec standard jesd22-a114-b. absolute maximum ratings
3 ? 2006 semtech corp. www.semtech.com power management SC480 test conditions: v in = 15v, vcca = vddp = vtten = en/psv = 5v, vddq = vttin = 1.8v, r ton = 1m . t amb = -40 to +85c. parameter conditions 25c -40c to 85c units min typ max min max vddq controller fb error comparator threshold (1) with adjustable resistor divider 1.500 1.485 1.515 v vddqs regulation threshold fb = agnd 2.5 2.475 2.525 v fb = vcca 1.8 1.782 1.818 v on-time rton = 1m , vddq = 1.8v 460 368 552 ns rton = 500k , vddq = 1.8v 265 212 318 minimum off-time 425 550 ns vddqs input resistance fb < 0.3v 80 k fb > 0.3v 91 k vddqs shutdown discharge resistance en/psv = gnd 16 fb leakage current -1.0 1.0 a vddq smart psave threshold 8 % vtt controller ref source current 10 ma ref sink resistance 50 k ref output accuracy iref = 0 to 10ma 900 882 918 mv shutdown discharge resistance (en/psv = gnd) vtt 0.25 ref 8 vtt output accuracy (with respect to ref) -2a < i vtt < 2a (9) 0 -40 +40 mv vtts leakage current -1.0 1.0 a current sensing ilim current dl high 10 9 11 a current comparator offset pgnd1 - ilim -10 10 mv zero-crossing threshold pgnd1 - lx, en/psv = 5v 5 mv vddq fault protection current limit (positive) (2) pgnd1 - lx, rlim = 5k 50 35 65 mv pgnd1 - lx, rlim = 10k 100 80 120 pgnd1 - lx, rlim = 20k 200 170 230 current limit (negative) pgnd1 - lx -125 -160 -90 mv output under-voltage fault with respect to fb regulation point -30 -35 -25 % electrical characteristics (cont.)
4 ? 2006 semtech corp. www.semtech.com power management SC480 power management test conditions: v in = 15v, vcca = vddp = vtten = en/psv = 5v, vddq = vttin = 1.8v, r ton = 1m . t amb = -40 to +85c. parameter conditions 25c -40c to 85c units min typ max min max under-voltage fault delay fb forced below uv v th 8 clks (3) under-voltage blank time from en high 440 clks (3) output over-voltage fault with respect to fb regulation point +16 +12 +20 % over-voltage fault delay fb above over-voltage threshold 5 s pgd low output voltage sink 1ma 0.1 v pgd leakage current fb in regulation, pgd = 5v 1 a pgd uv threshold with respect to fb regulation point -10 -12 -8 % pgd fault delay fb forced outside pgd window 5 s vcca under-voltage (uvlo) falling edge (hysteresis 100 mv) 4 3.70 4.35 v vtt fault protection uv lower threshold vtt w/rt ref -12 -16 -8 % ov upper threshold vtt w/rt ref +12 +8 +16 % fault shutdown delay vtt outside ov/uv window 50 s thermal shutdown (4)(5) 160 150 170 c inputs/outputs logic input low voltage en/psv low/low (disabled) 1.2 v vtten low (vtt disabled) 0.6 logic input high voltage en/psv low/high (enabled, psave disabled) 1.2 2.4 v vtten high (vtt enabled) 2.4 logic input high voltage en/psv high/high (enabled, psave enabled) 3.1 v en/psv input resistance sourcing 1.5 m sinking 1.0 m vtten leakage current -1 +1 a soft-start vddq soft-start ramp time en/psv high to pgd high 440 clks (3) vtt soft-start ramp rate (6) 5.5 mv/ s electrical characteristics (cont.)
5 ? 2006 semtech corp. www.semtech.com power management SC480 parameter conditions 25c -40c to 85c units min typ max min max fb input thresholds fb logic input low vddq set for 2.5v (ddr1) 0.3 v fb logic input high vddq set for 1.8v (ddr2) vcca - 0.7 v gate drives shoot-thru protection delay (4)(7) dh or dl rising 30 ns dl pull-down resistance dl low 0.8 dl sink current v dl = 2.5v 3.1 a dl pull-up resistance dl high 2 dl source current v dl = 2.5v 1.3 a dh pull-down resistance dh low, bst - lx = 5v 2 dh pull-up resistance (8) dh high, bst - lx = 5v 2 dh sink/source current v dh = 2.5v 1.3 a vtt pull-up resistance vtts < ref 0.25 vtt pull-down resistance vtts > ref 0.25 vtt peak sink/source current (9) 3.6 2.0 a test conditions: v in = 15v, vcca = vddp = vtten = en/psv = 5v, vddq = vttin = 1.8v, r ton = 1m . t amb = -40 to +85c. electrical characteristics (cont.) notes: 1) the vddq dc regulation level is higher than the fb error comparator threshold by 50% of the ripple voltage. 2) using a current sense resistor, this measurement relates to pgnd1 minus the source of the low-side mosfet. 3) clks = switching cycles, consisting of one high side and one low side gate pulse. 4) guaranteed by design. 5) thermal shutdown latches both outputs (vtt and vddq) off, requiring vcca or en/psv cycling to reset. 6) vtt soft-start ramp rate is limited to 5.5mv/ s typical. if the vddq/2 ramp rate is slower than 5.5mv/ sec, the vtt soft-start ramp will follow the vddq/2 ramp. 7) see shoot-through delay timing diagram on page 6. 8) semtech?s smartdriver? fet drive rst pulls dh high with a pull-up resistance of 10 (typ.) until lx = 1.5v (typ.). at this point, an additional pull-up device is activated, reducing the resistance to 2 (typical). this creates a softer turn-on with minimal power loss, eliminating the need for an external gate or boost resistor. 9) provided operation below t j(max) is maintained. vtt output current is also limited by internal mosfet resistance which is typically 0.25 at 25c and which increases with temperature, and by available source voltage (typically vddq/2).
6 ? 2006 semtech corp. www.semtech.com power management SC480 power management tplhdl tplhdh lx dl dl dh shoot-through delay timing diagram
7 ? 2006 semtech corp. www.semtech.com power management SC480 notes: 1) only available in tape and reel packaging. a reel contains 3000 devices. 2) this product is fully weee and rohs compliant. pin # pin name pin function 1 pgnd2 power ground for vtt output. connect to thermal pad and ground plane. 2 vtts sense pin for vtt. connect to vtt at the load. 3 vssa ground reference for analog circuitry. connect to thermal pad. 4ton this pin is used to sense vbat through a pull-up resistor, rton, which sets the top mosfet on-time. bypass this pin with a 1nf capacitor to vssa. 5 ref reference output. an internal resistor divider from vddqs sets this voltage to 50% vddq (nomi- nal). bypass this pin with a series 10 / 1 f to vssa. 6 vcca analog supply voltage input. use a 10 /1 f rc lter from +5v to vssa. 7 nc no connect. 8 vddqs sense input for vddq. used to set the on-time for the top mosfet and also to set ref/vtt. 9 fb feedback select input for vddq. see fb con guration table. 10 vtten enable pin for vtt. pull this pin low to disable vtt (ref remains present as long as vddq is present). 11 en/psv enable/power save input pin. tie to ground to disable vddq. tie to +5v to enable vddq and activate psave mode. float to enable vddq and activate continous conduction mode. if oated, bypass to vssa with a 10nf capacitor. 12 nc no connect. 13 pgd power good output for vddq. pgd is low if vddq is outside the power good thresholds. this pin is an open drain nmos output and requires an external pull-up resistor. 14,15 vddp +5v supply voltage input for the vddq gate drivers. device (2) package (1) SC480imltrt mlpq-24 SC480evb evaluation board pin description pgnd1 ilim pgnd1 pgd vddp vddp pgnd2 vssa vtts vcca ton ref vtt vttin bst dh lx dl nc vddqs fb en/psv nc vtten 23 2 1 4 3 21 22 19 20 24 6 5 8 7 10 9 12 11 17 18 15 16 13 14 SC480 mlp24 pin out t pin con guration ordering information
8 ? 2006 semtech corp. www.semtech.com power management SC480 power management enable pin status output status en/psv (1) vtten vddq (3) vtt (2) ref (2) 00 off, discharged (2)(3) off, discharged (2) off, discharged (2) 01 off, discharged (2)(3) off, discharged (2) off, discharged (2) 1 0 on off, high impedance on 1 1 on on on notes: 1) en/psv = 1 = en/psv high or oating. 2) typical discharge resistances: vtt = 0.25 . ref = 8 . 3) vddq is discharged via external series resistance which must be added to SC480 internal discharge resistance to calculate d ischarge times. this is separate from any external load on vddq. enable control logic the fb pin can be con gured for xed or adjustable output voltage as shown. fb con guration table fb vddq(v) vref & vtt (v) note gnd 2.5 vddqs/2 ddr1 vcca 1.8 vddqs/2 ddr2 fb resistors adjustable vddqs/2 1.5v < vddq < 3.0v pin description (cont.) 16 ilim current limit input pin. connect to drain of low-side mosfet for rds(on) sensing or the source for resistor sensing through a threshold sensing resistor. 17,18 pgnd1 power ground for vddq switching circuits. connect to thermal pad and ground plane. 19 dl gate drive output for the low side mosfet switch. 20 lx phase node - the junction between the top and bottom fets and the output inductor. 21 dh gate drive output for the high side mosfet switch. 22 bst boost capacitor connection for the high side gate drive. 23 vttin input supply for the high side switch for vtt regulator. decouple with a 1 f capacitor to pgnd2. 24 vtt output of the linear regulator. decouple with two (minimum) 10 f ceramic capacitors to pgnd2, locating them directly across pins 24 and 1. t thermal pad pad for heatsinking purposes. connect to ground plane using multiple vias. not connected internally.
9 ? 2006 semtech corp. www.semtech.com power management SC480 figure 1 block diagram faultmon sense por/ss vssa lo hi shoot thru control ov uv +16% -10% -30% sd pwm 1.5v vmon 1.5v ref -30% +16% -10% fb vddqs ton en/ psv ref vcca dschg pgd ilim pgnd1 dl vddp lx dh bst vtts otsd ton/ toff dschg vddqs vttrun ov sd lx dl dschg fedly vttpgd drvl drvh -12% +12% vddqs vcca por/ss vtten drvh novlp drvl otsd pgnd2 vtt vttin +12% -12%
10 ? 2006 semtech corp. www.semtech.com power management SC480 power management +5v bias supplies the SC480 requires an external +5v bias supply in addition to the battery. if stand-alone capability is required, the +5v supply can be generated with an external linear regulator. to minimize crosstalk, the controller has seven supply pins: vddp (2 pins), pgnd1 (2 pins), pgnd2, vcca and agnd. the controller requires its own agnd plane which should be tied by a single trace to the negative terminal of the output capacitor. all external components referenced to agnd in the schematic should then be connected to the agnd plane. the supply decoupling capacitor should be tied between vcca and agnd. a single 10 resistor should be used to decouple the vcca supply from the main vddp supply. pgnd can then be a separate plane which is not used for routing analog traces. all pgnd connections should connect directly to this plane with special attention given to avoiding indirect connections between agnd and pgnd which will create ground loops. as mentioned above, the agnd plane must be connected to the pgnd plane at the negative terminal of the output capacitor. the vddp input provides power to the upper and lower gate drivers. a decoupling capacitor for the vddp supply and pgnd is recommended. no series resistor between vddp and the 5 volt bias is required. pseudo-fixed frequency constant on-time pwm controller the pwm control method is a constant-on-time, pseudo- xed frequency pwm controller, see figure 1. the ripple voltage seen across the output capacitor?s esr provides the pwm ramp signal, eliminating the need for a current sense resistor. the on-time is determined by a one-shot whose period is proportional to output voltage, and inversely proportional to input voltage. a separate one- shot sets the minimum off-time (typically 425ns). on-time one-shot (t on ) the on-time one-shot comparator has two inputs. one input looks at the output voltage, while the other input samples the input voltage and converts it to a proportional current. this current charges an internal on-time capacitor. the ton time is the time required for this capacitor to charge from zero volts to vout, thereby making the on- time of the high-side switch directly proportional to output voltage and inversely proportional to input voltage. this implementation results in a nearly constant switching frequency without the need of a clock generator. ns 50 in v out v ) 3 37x10 (rton 12 3.3x10 on t ? ? 1 ? x x r ton is a resistor connected between the input supply and the ton pin. vddq/vtt enable & power-save the en/psv pin controls the vddq supply and the ref output (1/2 of vddq). vtten enables the vtt supply. the vtt and vddq supplies may be enabled independently. when en/psv is tied to vcca the vddq controller is enabled in power-save mode. when the en/psv pin is oated, an internal resistor divider activates the vddq controller with power-save disabled. if psave is enabled, the SC480 psave comparator looks for inductor current to cross zero on eight consecutive cycles. once observed, the controller enters power-save and turns off the low- side mosfet when the current crosses zero. to improve the ef ciency and add hysteresis, the on-time is increased by 20% in power-save. the ef ciency improvement at light loads more than offsets the disadvantage of slightly higher output ripple. if the inductor current does not cross zero on any switching cycle, the controller immediately exits power-save. since the controller counts zero crossings, the converter can sink current as long as the current does not cross zero on eight consecutive cycles. this allows the output voltage to recover quickly in response to negative load steps even when power-save is enabled. vddq voltage selection vddq voltage is set using the fb pin. grounding fb sets vddq to xed 2.5v. connecting fb to +5v sets vddq to xed 1.8v. vddq can also be adjusted from 1.5 to 3.0v using external resistors, see figure 2. the voltage at fb is then compared to the internal 1.5v reference. to vddq output capacitor to SC480 fb (pin 9) c r3 r2 figure 2 application information application information
11 ? 2006 semtech corp. www.semtech.com power management SC480 referencing figure 2, the equation for setting the output voltage is: 5 . 1 r3 2 r 1 v ) ( ut o x current limit circuit current limiting of the SC480 can be accomplished in two ways. the on-state resistance of the low-side mosfets can be used as the current sensing element, or a sense resistor in the low-side source can be used if greater ac- curacy is desired. rdson sensing is more ef cient and less expensive. in both cases, the r ilim resistor between the ilim pin and lx sets the over-current threshold. this resistor r ilim is connected to a 10 a current source within the SC480 which is turned on when the low-side mosfet turns on. when the voltage drop across the sense resistor or low-side mosfet equals the voltage across the r ilim resis- tor, current limit will activate. the high-side mosfet will not be allowed to turn on until the voltage drop across the sense element (resistor or mosfet) falls below the voltage across the r ilim resistor. the current sensing circuit actually regulates the inductor valley current, see figure 3. this means that if the current limit is set to 10a, the peak current through the inductor would be 10a plus the peak ripple current, and the average current through the inductor would be 10a plus 1/2 the peak-to-peak ripple current. i limit i load i peak inductor current time valley current - limit threshold point figure 3 application information d1 vout +5v +vin l1 + c1 q2 + c3 d2 r1 pgnd dl vddp ilim lx dh bst c2 q1 SC480 figure 4 the schematic of rds on sensing circuit is shown in figure 4 with r ilim = r1 and rds on of q2. similarly, for resistor sensing, the current through the lower mosfet and the source sense resistor develops a voltage that opposes the voltage developed across r ilim . when the voltage developed across the r sense resistor reaches voltage drop across r ilim, an over-current exists and the high-side mosfet will not be allowed to turn on. the over-current equation when using an external sense resistor is: sense r ilim r a ? 10 valley oc il x schematic of resistor sensing circuit is shown in figure 5 with r ilim = r1 and r sense = r4. figure 5 q1 q2 + c1 vout d1 r1 +5v l1 + c3 r4 d2 pgnd dl vddp ilim lx dh bst +vin c2 SC480
12 ? 2006 semtech corp. www.semtech.com power management SC480 power management power good output the vddq controller has a power good (pgd) output. power good is an open-drain output and requires a pull- up resistor. when the output voltage is +16%/-10% from its nominal voltage, pgd gets pulled low. it is held low until the output voltage returns to within +16%/-10% of nominal. pgd is also held low during start-up and will not be allowed to transition high until soft-start is over and the output reaches 90% of its set voltage. there is a 5 s delay built into the pgd circuit to prevent false transitions. output over-voltage protection when the vddq output exceeds 16% of its set voltage, the low-side mosfet is latched on. it stays latched and the smps stays off until the en/psv input is toggled or vcca is recycled. there is a 5 s delay built into the ov protection circuit to prevent false transitions. during a vddq ov shutdown, vtt is alive until vddq falls to typically 0.4v, at which point vtt is tri-stated. when vtt exceeds 12% above its set voltage, the vtt regulator will tristate. there is a 50 s delay to prevent false ov trips due to transients or noise. the vddq regulator continues to operate after vtt ov shutdown. the vtt ov condition is removed by toggling vtten or en/psv, or by recycling vcca. smart over-voltage protection in some applications, the active loads on vddq can actually leak current into vddq. if psave mode is enabled at very light loading, this leak can cause vddq to slowly rise and reach the ov threshold, causing a hard shutdown. to prevent this, the SC480 uses smart ovp to prevent this. when vddq exceeds 8% above nominal, dl drives high to turn on the low-side mosfet, which starts to draw current from vddq via the inductor. when vddq drops to the fb trip point, a normal ton switching cycle begins. this prevents a hard ov shutdown. output under-voltage protection when vddq falls 30% below its set point for eight clock cycles, the vddq output is shut off; the dl/dh drives are pulled low to tristate the mosfets, and the smps stays off until the enable input is toggled or vcca is recycled. when vtt is 12% below its set voltage the vtt output is tristated. there is a 50 s delay for vtt built into the uv protection circuits to prevent false transitions. por, uvlo and soft-start an internal power-on reset (por) occurs when vcca ex- ceeds 3v, resetting the fault latch and soft-start counter, and preparing the pwm for switching. vcca under-voltage lockout (uvlo), circuitry inhibits switching and tristates the drivers until vcca rises above 4.2v. at this time the circuit will come out of uvlo and begin switching and the soft- start circuit will progressively limit the output current over a pre-determined time period. the ramp occurs in four steps: 25%, 50%, 75% and 100%, thereby limiting the slew rate of the output voltage. there is 100mv of hysteresis built into the uvlo circuit and when vcca falls to 4.1v the output drivers are shutdown and tristated. mosfet gate drivers the dh and dl drivers are optimized for moderate, high- side, and larger low-side power mosfets. an adaptive dead-time circuit monitors the dl output and prevents the high-side mosfet from turning on until dl is fully off, and conversely, monitors the dh output and prevents the low- side mosfet from turning on until dh is fully off. (note: be sure there is low resistance and low inductance between the dh and dl outputs to the gate of each mosfet.) design procedure prior to designing a switch mode supply for a notebook com- puter, the input voltage, load current, switching frequency and inductor ripple current must be speci ed. input voltage range the maximum input voltage (vin max ) is determined by the highest ac adaptor voltage. the minimum input voltage (vin min ) is determined by the lowest battery voltage after accounting for voltage drops due to connectors, fuses and battery selector switches. maximum load current there are two values of load current to consider: continu- ous load current and peak load current. continuous load current has more to do with thermal stresses and there- fore drives the selection of input capacitors, mosfets and commutation diodes. peak load current determines instantaneous component stresses and ltering require- ments such as, inductor saturation, output capacitors and design of the current limit circuit. application information (cont.)
13 ? 2006 semtech corp. www.semtech.com power management SC480 application information (cont.) switching frequency switching frequency determines the trade-off between size and ef ciency. higher frequency increases switch- ing losses in the mosfets, since losses are a function of f*vin2. knowing the maximum input voltage and budget for mosfet switches usually dictates the nal design. inductor ripple current low inductor values result in smaller size, but create high- er ripple current and are less ef cient because of the high ac current owing in the inductor. higher inductor values do reduce the ripple current and are more ef cient, but are larger and more costly. the selection of the ripple cur- rent is based on the maximum output current and tends to be between 20% to 50% of the maximum load current. again, cost, size and ef ciency all play a part in the selec- tion process. stability considerations unstable operation shows up in two related but distinctly different ways: double pulsing and fast-feedback loop in- stability. double-pulsing occurs due to noise on the output or because the esr is too low, causing insuf cient voltage ramp in the output signal. this causes the error ampli er to trigger prematurely after the 400ns minimum off-time has expired. double-pulsing will result in higher ripple voltage at the output, but in most cases is harmless. in some cases, however, double-pulsing can indicate the presence of loop instability, which is caused by insuf cient esr. one simple way to solve this problem is to add some trace resistance in the high current output path. a side effect of doing this is output voltage droop with load. another way to eliminate doubling-pulsing is to add a 10pf capacitor across the upper feedback resistor divider network. this is shown in figure 6, by capacitor c4 in the schematic. this capacitance should be left out until con rmation that double-pulsing ex- ists. adding this capacitance will add a zero in the transfer function and should eliminate the problem. it is best to leave a spot on the pcb in case it is needed. loop instability can cause oscillations at the output as a response to line or load transients. these oscillations can trip the over-voltage protection latch or cause the output voltage to fall below the tolerance limit. the best way for checking stability is to apply a zero to full load transient and observe the output voltage ripple envelope for overshoot and ringing. over one cycle of ringing after the initial step is a sign that the esr should be increased. fbk +5v + c1 8 9 10 11 12 13 14 pgnd dl vddp ilim lx dh bst +vin r2 c2 q2 l1 q1 r1 0.5v - 5.5v c4 10pf d2 d1 r3 + c3 SC480 figure 6 SC480 esr requirements the constant on-time control used in the SC480 regulates the ripple voltage at the output capacitor. this signal consists of a term generated by the output esr of the capacitor and a term based on the increase in voltage across the capacitor due to charging and discharging during the switching cycle. the minimum esr is set to generate the required ripple voltage for regulation. for most applications the minimum esr ripple voltage is dominated by pcb layout and the properties of sp or poscap type output capacitors. for applications using ceramic output capacitors, the absolute minimum esr must be considered. if the esr is low enough the ripple voltage is dominated by the charging of the output capacitor. this ripple voltage lags the on-time due to the lc poles and can cause double pulsing if the phase delay exceeds the off-time of the converter. referring to figure 5 on page 11, the equation for the minimum esr as a function of output capacitance and switching frequency and duty cycle is: ? ? ? ? 1 ? x x x x ? 1 ? x x ? 1 ? ! d 1 2 fs cout 2 fs 200000 - fs 3 1 1.5v vout esr
14 ? 2006 semtech corp. www.semtech.com power management SC480 power management application information (cont.) dropout performance the output voltage adjust range for continuous-conduction operation is limited by the xed 400ns (typical) minimum off-time one-shot. for best dropout performance, use the slowest on-time setting of 200khz. when working with low input voltages, the duty-factor limit must be calculated using worst-case values for on and off times. the ic duty- factor limitation is given by: (max) toff (min) ton (min) ton duty be sure to include inductor resistance and mosfet on- state voltage drops when performing worst-case dropout duty-factor calculations. SC480 system dc accuracy (vddq controller) three ic parameters affect vddq accuracy: the internal 1.5v reference, the error comparator offset voltage, and the switching frequency variation with line and load. the internal 1%, 1.5v reference contains two error components, a 0.5% dc error and a 0.5% supply and temperature error. the error comparator offset is trimmed so that it trips when the feedback pin is nominally 1.5 volts +/-1% at room temperature. the comparator offset trim compensates for any dc error in the reference. thus, the percentage error is the sum of the reference variation over supply and temperature and the offset in the error comparator, or 1.5% total. the on-time pulse in the SC480 is calculated to give a pseudo- xed frequency. nevertheless, some frequency variation with line and load can be expected. this variation changes the output ripple voltage. because constant on- time converters regulate to the valley of the output ripple, ? of the output ripple appears as a dc regulation error. for example, if the output ripple is 50mv with vin = 6 volts, then the measured dc output will be 25mv above the comparator trip point. if the ripple increases to 80mv with vin = 25 volts, then the measured dc output will be 40mv above the comparator trip. the best way to minimize this effect is to minimize the output ripple. to compensate for valley regulation it is often desirable to use passive droop. take the feedback directly from the output side of the inductor, incorporating a small amount of trace resistance between the inductor and output capacitor. this trace resistance should be optimized so that at full load the output droops to near the lower regulation limit. passive droop minimizes the required output capacitance because the voltage excursions due to load steps are reduced. board components and layout also in uence dc accuracy. the use of 1% feedback resistors contributes up to 1% error. if tighter dc accuracy is required use 0.1% feedback resistors. the output inductor value may change with current. this will change the output ripple and thus the dc output voltage (it will not change the frequency). switching frequency variation with load can be minimized by choosing lower rds on mosfets. high rds on mosfets will cause the switching frequency to increase as the load current increases. this will reduce the ripple and thus the dc output voltage. this inherent droop should be considered when deciding if passive droop is required, or if passive droop is desired in order to further reduce the output capacitance. output dc accuracy (vtt output) the vtt accuracy compared to vddq is determined by two parameters: the ref output accuracy, and the vtt output accuracy with respect to ref. the ref output is generated internally from the vddqs (sense input), and tracks vddqs with 2% accuracy. this ref output becomes the reference for the vtt regulator. the vtt regulator then tracks ref within +/-40mv (typically zero). the total vtt/vddq tracking accuracy is then: 40mv 0.02 2 vddqs error vtt r r x ddr reference buffer the reference buffer is capable of sourcing 10ma. the reference buffer has a class a output stage and therefore will not sink signi cant current; there is an internal 50 k (typical) pulldown to ground. if higher current sinking is required, an external pulldown resistor should be added. make sure that the ground side of this pulldown is tied to the vtt ground plane near the pgnd2 pin.
15 ? 2006 semtech corp. www.semtech.com power management SC480 for stability, place a 10 /1 f series combination from ref to vssa. if ref load capacitance exceeds 1 f, place at least 10 in series with the load capacitance to prevent instability. it is possible to use only one 10 resistor, by connecting the load capacitors in parallel with the 1 f, and connecting the load ref to the capacitor side of the 10 resistor. (see the typical application circuit on page 1.) note that this resistor creates an error term when ref has a dc load. in most applications this is not a concern since the dc load on ref is negligible. design procedure prior to designing a switching output and making com- ponent selections, it is necessary to determine the input voltage range and output voltage speci cations. to dem- onstrate the procedure, the output for the schematic in figure 7 on page 18 will be designed. the maximum input voltage (v bat(max) ) is determined by the highest ac adaptor voltage. the minimum input voltage (v bat(min) ) is determined by the lowest battery voltage af- ter accounting for voltage drops due to connectors, fuses and battery selector switches. for the purposes of this design example we will use a vbat range of 8v to 20v to design vddq. four parameters are needed for the design: nominal output voltage, v out . we will use 1.8v with internal feedback resistors (fb pin tied to vcca). static (or dc) tolerance, tol st (we will use +/-2%). transient tolerance, tol tr and size of transient (we will use +/-8% for a 10a to 5a load release for this demonstration). maximum output current, i out (we will design for 10a). switching frequency determines the trade-off between size and ef ciency. increased frequency increases the switching losses in the mosfets, and losses are a function of vbat 2 . knowing the maximum input voltage and budget for mosfet switches usually dictates where the design ends up. the default r ton values of 1m and 715k are suggested only as a starting point. the rst thing to do is to calculate the on-time, t on , at v bat(min) and v bat(max) , since this depends only upon v bat , v out and rt on . 1. 2. 3. 4. s 9 10 50 ) min ( bat v out v 3 10 37 ton r 12 10 3.3 n) on_vbat(mi t x ? ? ? o ? ? ? a x x x x and, s 9 10 50 ) max ( bat v out v 3 10 37 ton r 12 10 3.3 x) on_vbat(ma t x ? ? ? o ? ? ? a x x x x from these values of t on we can calculate the nominal switching frequency as follows: hz n) on_vbat(mi t bat(min) v out v (min) sw_vbat f ? 1 ? x and, hz x) on_vbat(ma t bat(max) v out v (max) sw_vbat f ? 1 ? x t on is generated by a one-shot comparator that samples v bat via r ton , converting this to a current. this current is used to charge an internal 3.3pf capacitor to v out . the equations above re ect this along with any internal com- ponents or delays that in uence t on . for our example we select r ton = 1m : t on_vbat(min) = 820ns and, t on_vbat(max) = 358ns f sw_vbat(min) = 274khz and f sw_vbat(max) = 251khz now that we know t on we can calculate suitable values for the inductor. to do this we select an acceptable inductor ripple current. the calculations below assume 50% of i out which will give us a starting place. h out i 0.5 (min) on_vbat t out v bat(min) v (min) vbat l ? 1 ? x x and, h out i 0.5 x) on_vbat(ma t out v bat(max) v (max) vbat l ? 1 ? x x for our example: l vbat(min) = 1.02 h and l vbat(max) = 1.30 h, application information (cont.)
16 ? 2006 semtech corp. www.semtech.com power management SC480 power management where err tr is the transient output tolerance. for this case, i trans is the load transient of 5a (10a - 5a). for our example: err tr = 144mv and err dc = 18mv, therefore, r esr_tr(max) = 17.6m for a full 5a load transient. we will select a value of 6m maximum for our design, which would be achieved by using two 12m output ca- pacitors in parallel. now that we know the output esr we can calculate the output ripple voltage: p p v ) min ( t ripple_vba i esr r ) min ( t ripple_vba v x and, p p v ) max ( t ripple_vba i esr r ) max ( t ripple_vba v x for our example: v ripple_vbat(max) = 20mv p-p and v ripple_vbat(min) = 26mv p-p note that in order for the device to regulate in a controlled manner, the ripple content at the feedback pin, v fb , should be approximately 15mv p-p at minimum v bat , and worst case no smaller than 10mv p-p . note that the voltage ripple at fb is smaller than the voltage ripple at the output capaci- tor, due to the resistor divider. also, when using internal feedback (fb pin tied to 5v or gnd), the fb resistor di- vider is actually inside the ic. if v ripple_vbat(min) as seen at the fb point is less than 15mv p-p - whether internal or ex- ternal fb is used - the above component values should be revisited in order to improve this. for our example, since the internal divider reduces the ripple signal by a factor of (1.5v/1.8v), the internal fb ripple values are then 17mv and 22mv, which is above the 15mv minimum. when using external feedback, and with vddq greater than 1.5v, a small capacitor, c top , can be used in parallel with the top feedback resistor, r top , in order to ensure that ripple at vfb is large enough. c top should not be greater than 100pf. the value of c top can be calculated as fol- lows, where r bot is the bottom feedback resistor. firstly calculating the value of z top required: application information (cont.) we will select an inductor value of 1.5 h to reduce the ripple current, which can be calculated as follows: p p a l ) min ( vbat on_ t out v ) min ( bat v ) min ( bat ripple_v i x ? 1 ? and, p p a l ) max ( vbat on_ t out v ) max ( bat v ) max ( bat ripple_v i x ? 1 ? for our example: i ripple_vbat(min) = 3.39a p-p and i ripple_vbat(max) = 4.34a p-p from this we can calculate the minimum inductor current rating for normal operation: (min) a 2 ) max ( t ripple_vba i ) max ( out i ) min ( inductor i for our example: i inductor(min) = 12.2a (min) next we will calculate the maximum output capacitor equivalent series resistance (esr). this is determined by calculating the remaining static and transient tolerance allowances. then the maximum esr is the smaller of the calculated static esr (r esr_st(max) ) and transient esr (r esr_tr(max) ): ohms ) max ( bat v _ ripple i 2 dc err st err ) max ( st _ esr r x where err st is the static output tolerance and err dc is the dc error. the dc error will be 1% plus the tolerance of the internal feedback. (use 2% for external feedback, which is 1% plus another 1% for the external resistors.) for our example: err st = 36mv and, err dc = 18mv, therefore, r esr_st(max) = 8.3m ohms 2 ) max ( t ripple_vba i trans i dc err tr err ) max ( tr esr_ r ? ? 1 ? ? 1 ?
17 ? 2006 semtech corp. www.semtech.com power management SC480 ohms 0.015 v 0.015 r z ) min ( t ripple_vba bot top x secondly calculating the value of c top required to achieve this: f ) min ( vbat _ sw f 2 top r 1 top z 1 top c x x ? ? 1 ? since our example uses internal feedback ,this method cannot be used, however the voltage seen at the internal fb point is already greater than 15mv. next we need to calculate the minimum output capaci- tance required to ensure that the output voltage does not exceed the transient maximum limit, poslim tr , starting from the actual static maximum, v out_st_pos , when a load release occurs: v dc err out v out_st_pos v for our example: v out_st_pos = 1.818v, v tr tol out v tr poslim x where tol tr is the transient tolerance. for our example: poslim tr = 1.944v, the minimum output capacitance is calculated as fol- lows: a 2 ) max ( t ripple_vba i ) max ( out i init i and, f 2 out_st_pos v 2 tr poslim 2 ifinal 2 iinit l out(min) c x this calculation assumes the condition of a full-load to no- load step transient occurring when the inductor current is at its highest. the capacitance required for smaller tran- sient steps my be calculated by substituting the desired current for the i nal term. in this case i nal is set for 5a. for our example: c out(min) = 392 f. we will select 440 f, using two 220 f, 12m capacitors in parallel. next we calculate the rms input ripple current, which is largest at the minimum battery voltage: rms min _ bat out out ) min ( bat out ) rms ( in a v i v v v i x x for our example: i in(rms) = 4.17a rms input capacitors should be selected with suf cient ripple current rating for this rms current, for example a 10 f, 1210 size, 25v ceramic capacitor can handle approxi- mately 3a rms . refer to manufacturer?s data sheets and derate appropriately. finally, we calculate the current limit resistor value. as de- scribed in the current limit section, the current limit looks at the ?valley current?, which is the average output cur- rent minus half the ripple current. a 2 ) min ( t ripple_vba i out i valley i the ripple at low battery voltage is used because we want to make sure that current limit does not occur under nor- mal operating conditions. ohms 6 10 10 1.4 (on) ds r 1.2 valley i ilim r x x x x for our example: i valley = 8.31a, r ds(on) = 4m , giving r ilim = 5.62k application information (cont.)
18 ? 2006 semtech corp. www.semtech.com power management SC480 power management thermal considerations the junction temperature of the device may be calculated as follows: t j = t amb + ja where t j is the junction temperature, t amb is the ambient temperature, pd is the total SC480 device dissipation, the SC480 device dissipation can be determined using: pd = vcca ? icca + vddp ? iddp + vtt ? | itt | the rst two terms are losses for the analog and gate drive circuits and generally do not present a thermal problem. typical icca (vcca operating current) is roughly 1.5ma, which creates 7.5mw loss from the 5v vcca supply. the vddp supply current is used to drive the mosfets and can be much higher, on the order of 30ma, which can create up to 150mw of dissipation. the last term, vtt * |itt|, is the most signi cant term from a thermal standpoint. the vtt regulator is a linear device and will dissipate power proportional to the vtt current and the voltage drop across the regulator. if vtt = vddq/2, then the voltage drop across the regulator is always vddq2, regardless of whether the regulator is sinking or sourcing current. in either case the power lost in the vtt regulator is vtt * |itt|. the average or long- term value for itt should be used. the thermal resistance of the mlpq package is affected by pcb layout and the available ground planes and vias which conduct heat away. a typical value is 29c/watt. example: icca = 1.5ma iddp = 25ma vcca = vddp = 5v vtt = 1.25v itt = 0.75a (average) ambient = 45 degrees c thermal resistance = 29 p d = 5v ? 0.0015 a + 5v ? 0.025a + 0.9v ? |0.75|a p d = 0.808w t j = t amb + p d ? t ja = 45 + 0.808w ? 29c/w = 68.4c : application information (cont.) layout guidelines one (or more) ground planes are recommended to minimize the effect of switching noise and copper losses, and maximize heat dissipation. the ic ground reference, vssa, should be connected to pgnd1 and pgnd2 as a star connection at the thermal pad, which in connects using 4 vias to the ground plane. all components that are referenced to vssa should connect to it directly on the chip side, and not through the ground plane. vddq: the feedback trace must be kept far away from noise sources such as switching nodes, inductors and gate drives. route the feedback trace in a quiet layer if possible, from the output capacitor back to the chip. chip supply decoupling capacitors (vcca, vddp) should be located next to the pins (vcca/vssa, vddp/pgnd1) and connected directly to them on the same side. vtt: because of the high bandwidth of the vtt regulator, proper component placement and routing is essential to prevent unwanted high-frequency oscillations which can be caused by parasitic inductance and noise. the input capacitors should be located at the vtt input pins (vttin and pgnd2), as close as possible to the chip to minimize parasitics. output capacitors should be directly located at the vtt output pins (vtt and pgnd2). the routing of the feedback signal vtts is critical. the trace from vtts (pin 2) should be connected directly to the output capacitor that is farthest from vtt (pin24); route this signal away from noise sources such as the vddq power train or high- speed digital signals. the switcher power section should connect directly to the ground plane(s) using multiple vias as required for current handling (including the chip power ground connections). power components should be placed to minimize loops and reduce losses. make all the connections on one side of the pcb using wide copper lled areas if possible. do not use ?minimum? land patterns for power components. minimize trace lengths between the gate drivers and the gates of the mosfets to reduce parasitic impedances (and mosfet switching losses); the low-side mosfet is most critical. maintain a length to width ratio of <20:1 for gate drive signals. use multiple vias as required by current handling requirement (and to reduce parasitics) if routed on more than one layer. current sense connections must always be made using kelvin connections to ensure an
19 ? 2006 semtech corp. www.semtech.com power management SC480 application information (cont.) accurate signal. the layout can be generally considered in three parts; the control section referenced to vssa, the vtt output, and the switcher power section. looking at the control section rst, locate all components referenced to vssa on the schematic and place these components at the chip. connect vssa using a wide (>0.020?) trace. very little current ows in the chip ground therefore large areas of copper are not needed. connect the vssa pin directly to the thermal pad under the device as the only connection from pgnd1 and pgnd2 from vssa. decoupling capacitors for vcca/vssa and vddp/pgnd1 should be placed is as close as possible to the chip. the feedback components connected to fb, along with the vddq sense components, should also be located at the chip. the feedback trace from the vddq output should route from the top of the output capacitors, in a quiet layer back to the fb components. next, looking at the switcher power section, there are a few key guidelines to follow: there should be a very small input loop, well decoupled. the phase node should be a large copper pour, but still compact since this is the noisiest node. input power ground and output power ground should not connect directly, but through the ground planes instead. 1. 2. 3. finally, connecting the control and switcher power sections should be accomplished as follows: route vddq feedback trace in a ?quiet? layer, away from noise sources. route dl, dh and lx (low side fet gate drive, high side fet gate drive and phase node) to the chip using wide traces with multiple vias if using more than one layer. these connections are to be as short as possible for loop minimization, with a length to width ratio less than 20:1 to minimize impedance. dl is the most critical gate drive, with power ground as its return path. lx is the noisiest node in the circuit, switching between vbat and ground at high frequencies, thus should be kept as short as practical. dh has lx as its return path. bst is also a noisy node and should be kept as short as possible. connect pgnd1 pins on the chip directly to the vddp decoupling capacitor and then drop vias directly to theground plane. locate the current limit resistor at the chip with a kelvin connection to the phase node. 1. 2. 3. 4.
20 ? 2006 semtech corp. www.semtech.com power management SC480 power management application information (cont.) adjustable 1.5v-3.0v: connect to divider network 1210 5v r5 10r c15 1uf vtt c16 0.1uf q1 irf7811 d1 mbr0530 c2 10uf/25v vbat r2 1meg l1 1.5uh + c9* 220uf/12m vddq vtt_en c11 0.1uf r3 10r c14 1uf vbat c13 1nf c4 1uf en/psv c5 10uf pgnd2 1 vtts 2 vssa 3 ton 4 ref 5 vcca 6 nc 7 vtten 10 fb 9 lx 20 dl 19 pgnd1 18 pgnd1 17 ilim 16 vddp 15 vddp 14 nc 12 en/psv 11 vddqs 8 pgd 13 vttin 23 vtt 24 bst 22 dh 21 pad u1 SC480 r4 10k c7 10uf c3 10uf/25v vddq q2 irf7832 5v pad + c10* 220uf/12m c1 0.1uf 5v pgood r1 5.62k c12 1uf c6 10uf *sanyo 4tpl220mc c8 0.1uf vddq 0805 1.8v fixed: connect to 5v vishay ihlp-5050 0805 0805 1210 ref 2.5v fixed: connect to vssa figure 7 - reference design
21 ? 2006 semtech corp. www.semtech.com power management SC480 typical characteristics 1.8v ef ciency vs. output current powersave mode 1.8v ef ciency vs. output current continuous conduction mode 2.5v ef ciency vs. output current powersave mode 50% 60% 70% 80% 90% 100% 0246810 i out (a) efficiency (%) vbat = 20 vbat = 10 50% 60% 70% 80% 90% 100% 0246810 i out (a) efficiency (%) vbat = 20 vbat = 10 50% 60% 70% 80% 90% 100% 0246810 i out (a) efficiency (%) vbat = 10 vbat = 20 50% 60% 70% 80% 90% 100% 0246810 i out (a) efficiency (%) 2.5v ef ciency vs. output current continuous conduction mode vbat = 20 vbat = 10 1.5v ef ciency vs. output current powersave mode 1.5v ef ciency vs. output current continuous conduction mode 50% 60% 70% 80% 90% 100% 0246810 i out (a) efficiency (%) vbat = 20 vbat = 10 50% 60% 70% 80% 90% 100% 0246810 i out (a) efficiency (%) vbat = 10 vbat = 20
22 ? 2006 semtech corp. www.semtech.com power management SC480 power management typical characteristics (cont.) load transient response, 0 to 5a, psave mode load transient response, 0 to 5a, continuous conduction mode load transient response, 5 to 0a, psave mode load transient response, 5 to 0a, continuous conduction mode load transient response, 5 to 10a load transient response, 10 to 5a
23 ? 2006 semtech corp. www.semtech.com power management SC480 typical characteristics (cont.) vtt load transient response, 1a sink/source, psave mode vtt load transient response, 1a sink/source, continuous conduction mode startup (psv), en/psv going high startup (psv), en/psv going low, vddq = 5a
24 ? 2006 semtech corp. www.semtech.com power management SC480 power management outline drawing - mlpq 24 (4x4mm) e1 e bxn d/2 1 2 n e1 .100 .106 .110 2.55 2.70 2.80 pin 1 indicator 4.15 3.85 4.00 4.15 3.85 .157 .151 .163 .151 .163 aaa c a c (laser mark) d e b a1 a a2 seating plane lxn e/2 bbb c a b d1 inches .020 bsc b .007 bbb aaa n d1 e l e d .011 .100 dim a1 a2 a min .000 - .031 0.30 0.18 .012 0.25 .010 0.50 2.80 0.30 2.55 .004 .004 24 .016 .157 .106 .020 .110 0.10 0.10 24 0.40 4.00 2.70 0.50 bsc millimeters max 0.05 - 1.00 dimensions min 0.00 - nom (.008) .035 .001 max .002 - .040 nom 0.80 0.02 (0.20) 0.90 controlling dimensions are in millimeters (angles in degrees). coplanarity applies to the exposed pad as well as the terminals. notes: 2. 1.
25 ? 2006 semtech corp. www.semtech.com power management SC480 land pattern - mlpq 24 (4x4mm) this land pattern is for reference purposes only. consult your manufacturing group to ensure your notes: 1. dim x y h k p c g millimeters inches (3.95) .010 .033 .122 .021 .106 .106 (.155) 0.25 0.85 2.70 0.50 2.70 3.10 dimensions company's manufacturing guidelines are met. 4.80 .189 z k g z h (c) x p www.semtech.com semtech corporation power management products division 200 flynn road, camarillo, ca 93012 phone: (805) 498-2111 fax: (805) 498-3804 contact information

▲Up To Search▲

Price & Availability of SC480

	To Download SC480 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .